1. Field of the Invention
The present invention relates to a gate turnoff thyristor and a method of fabricating the same, and more particularly, it relates to an improvement for reducing a gate trigger current while maintaining a withstand voltage.
2. Background of the Invention
A gate turnoff thyristor (hereinafter referred to as a GTO) is a thyristor which can be not only turned on but turned off by proper application of a gate current. FIG. 54 illustrates a sectional structure of a conventional GTO 50. In this GTO 50, five semiconductor layers are formed in a substantially flat plate type silicon semiconductor substrate 60. Namely, a p emitter layer 11 containing a p-type impurity, an n buffer layer 12 containing an n-type impurity in high concentration, an n base layer 13 containing an n-type impurity in low concentration, a p base layer 14 containing a p-type impurity, and an n emitter layer 15 containing an n-type impurity are successively stacked from a lower major surface toward an upper major surface of the semiconductor substrate 60, thereby forming the so-called pn.nu.pn structure.
The p emitter layer 11 is exposed on the lower major surface of the semiconductor substrate 60, while the n buffer layer 12 which is stacked on the p emitter layer 11 is selectively exposed on a portion immediately under the n emitter layer 15. An anode electrode 1 which is one of main electrodes serving as paths for the main current of the device is formed on the lower major surface of the semiconductor substrate 60, and this anode electrode 1 is in ohmic contact with the p emitter layer 11 as well as with the exposed surface of the n buffer layer 12. Namely, this GTO 50 is an exemplary GTO having the so-called anode short structure provided with an n.sup.+ buffer.
On the other hand, an upper surface of the p base layer 14 is exposed on the upper major surface of the semiconductor substrate 60, while the n emitter layer 15 which is selectively formed on the p base layer 14 upwardly projects from the upper major surface of the semiconductor substrate 60. A cathode electrode 2 which is another major electrode paired with the anode electrode 1 is formed on an upper surface of the n emitter layer 15, to be in ohmic contact with the n emitter layer 15. Further, gate electrodes 3 serving as paths for the gate current are formed on the exposed surface of the p base layer 14, to be in ohmic contact with the p base layer 14.
This GTO 50 can be equivalently expressed in a circuit diagram shown in FIG. 55. Namely, the GTO 50 has such a structure that a pnp transistor and an npn transistor are coupled with each other. Reflecting that a part of the n buffer layer 12 is connected to the anode electrode 1, a base and an emitter of the pnp transistor is short-circuited by a resistance corresponding to a sheet resistance R.sub.0 of the n buffer layer 12. With reference to the equivalent circuit diagram shown in FIG. 55, the operation of the GTO 50 is now described.
In order to use the GTO 50, an external power source is first connected to apply a bias voltage across the anode electrode 1 and the cathode electrode 2 in a positive direction. In this state, a positive gate current I.sub.G is supplied from the gate electrode 3. At this time, the gate current I.sub.G serves as a base current of the npn transistor which is formed by the n buffer layer 12 and the n base layer 13, the p base layer 14 and the n emitter layer 15 until the same reaches a sufficiently high level, whereby a collector current I.sub.C of this npn transistor flows from the anode electrode 1 to the cathode electrode 2.
This collector current I.sub.C directly flows in the n buffer layer 12 from the anode electrode 1 through the contact surface with the n buffer layer 12. Thus, a voltage E.sub.0 corresponding to a voltage drop which is developed in the sheet resistance R.sub.0 through the flow of the collector current I.sub.C is applied across the p emitter layer 11 and the n buffer layer 12.
This voltage E.sub.0 serves as a base-to-emitter voltage of the pnp transistor which is formed by the p emitter layer 11, the n buffer layer 12 and the n base layer 13, and the p base layer 14. When the gate current I.sub.G reaches a sufficiently high level and hence the base-to-emitter voltage E.sub.0 exceeds a forward voltage which is specific to the junction between the p emitter layer 11 and the n buffer layer 12, therefore, an anode current I.sub.A flows from the anode electrode 1 to the p emitter layer 11.
This anode current I.sub.A increases the base current of the npn transistor, whereby the collector current I.sub.C of the npn transistor is increased. Consequently, a base current of the pnp transistor is increased, to further increase the anode current I.sub.A. Namely, the anode current I.sub.A is steadily increased by a positive feedback action of the two transistors, whereby the GTO 50 finally conducts. Namely, the GTO 50 is turned on.
In this GTO 50, the n buffer layer 12 prevents a depletion layer from reaching the anode electrode 1, thereby increasing the withstand voltage of the GTO 50. The n buffer layer 12 also reduces the resistance upon such conduction of the GTO 50, i.e., an ON-state resistance, thereby advantageously reducing stationary loss. These effects further remarkably appear as the impurity concentration in the n buffer layer 12 is increased.
When the n buffer layer 12 has high impurity concentration, however, the aforementioned sheet resistance R.sub.0 is reduced and hence the base-to-emitter voltage E.sub.0 across the p emitter layer 11 and the n buffer layer 12 is reduced in response thereto. Consequently, the gate current I.sub.G which is required for turning on the GTO 50, i.e., a gate trigger current I.sub.GT, is disadvantageously increased. When the gate trigger current I.sub.GT is thus increased, an initial turnon region in a process of turning on the GTO 50, i.e., a region implementing conduction in an initial turnon time, is reduced and hence a resistance, called a di/dt resistance, against an abruptly rising ON-state current which is generated in the initial turnon time is reduced. If the initial turnon region is reduced, further, power loss is increased in this region and the turnon time is increased, to increase turnon loss.
In the conventional GTO 50, as hereinabove described, it is difficult to compatibly implement improvement in withstand voltage and ON-state resistance as well as reduction in turnon loss and improvement in di/dt resistance.